(a) Field of the Invention
The present invention relates to a technique of mounting an electronic component such as a semiconductor device on a wiring board, and more particularly to a wiring board (hereinafter also referred to as “package” for the sake of convenience) adapted to detachably mount an electronic component thereon, and to a method of manufacturing the same.
(b) Description of the Related Art
For surface mounting of an electronic component (a chip) such as a semiconductor device on a wiring board (a package), wire bonding, flip chip bonding or the like is used as means for providing an electrical connection between the chip and the package. The wire bonding requires a bonding area (an area having an arrangement of pads for wire connections) around the chip mounted on the package, resulting in the package with a correspondingly large area, while the flip chip bonding is effective in a reduction in size of the package, since this bonding permits mounting of the chip on the package with a conductive bump sandwiched therebetween and thus eliminates the need for the bonding area around the chip.
In an electronic component device of such a flip chip bonding type, the electrical connection between the chip and the package is accomplished by using: one method (namely, bonding using the same metal) that involves providing bumps made of the same metallic material on both the chip and the package, or alternatively providing a metal bump only on the chip, and bonding the chip and the package together with the bumps made of the same metal sandwiched therebetween; or another method (namely, bonding using different metals) that involves providing bumps made of different metallic materials on the chip and the package, respectively, and bonding the chip and the package together with the bumps made of different metals. For example, the bonding using the same metal includes bonding of a solder bump to a solder bump, while the bonding using different types of metals include bonding of a copper (Cu) bump to a solder bump, bonding of a gold (Au) bump to a solder bump, and the like.
An example of techniques related to the above-mentioned conventional techniques is disclosed in Japanese unexamined Patent Publication (JPP) (Kokai) 2000-183507. The technique disclosed in this publication involves vertically arranging conductive columnar elements on electrode pads formed on the surface of an object to be mounted; vertically arranging conductive cylindrically-shaped receiving portions configured to detachably fit the columnar elements on lands formed on the surface of a packaging board; and inserting the columnar elements into the corresponding cylindrically-shaped receiving portions, respectively, thereby mounting the object to be mounted on the packaging board. Also, another example of the pertinent technique is disclosed in JPP (Kokai) 10-163267. The technique disclosed in this publication involves forming conductive portions having holes on pads of a base material; forcedly fitting bumps of workpieces into the holes; and engaging projections inwardly projecting in the upper portions of the conductive portions, with edges formed on the bumps, thereby preventing the bumps from being disengaged from the holes. Further, another example of the technique is disclosed in JPP (Kokai) 1-226160. The technique disclosed in this publication provides a terminal device for electronic component connection, formed by connecting electrodes of an electronic component to electrodes on a substrate, in which recesses and projections are provided by a photo-work method between the substrate and the electronic component to thereby form terminals to be connected to the electrodes. Then, of these terminals, the terminals on the part of the projections are fitted in the terminals on the part of the recesses.
As mentioned above, in the conventional electronic component device of the flip chip bonding type, the electrical connection between the chip and the package is accomplished by the bonding using the bumps made of the same metal, or the bonding using the bumps made of different metals. Generally, such an electronic component device undergoes, prior to shipment, an electrical test on its detailed functions (a product reliability evaluation) with the chip mounted on the package. However, the conventional electronic component device of the flip chip bonding type encounters problems as given below when subjected to such a test for reliability evaluation.
Specifically, the bonding using different metals involves the formation of an alloy layer at the bonding interface between the metals. For example, as shown in FIG. 9A, assuming that the bonding involves: providing solder bumps BP1 (containing tin (Sn) as the main metal) respectively on pad portions 52 (e.g., copper (Cu)/nickel (Ni)/gold (Au) plating layers) exposed from portions of a protection film 51 (e.g., a solder resist layer) of a wiring board 50; providing copper (Cu) bumps BP2 respectively on pad portions 62 (e.g., aluminum (Al) conductor layers) exposed from portions of a protection film 61 (e.g., a passivation film) of a chip 60; and bonding the metal bumps BP1 and BP2 together by melting or the like. In this case, alloy layers (Cu—Sn) BM are formed, respectively, at the bonding interfaces between the metal bumps BP1 and BP2.
The alloy layer BM has the following problems. Because of being generally brittle to thermal stress, the alloy layer BM may possibly break off under a temperature cyclic test (e.g., a test to determine a change in product characteristics caused by repeated cycles of changing the temperature in a range between a temperature of +125° C. to +150° C. and a temperature of −40° C. to −65° C.) after chip mounting. In some cases, “break-off” may possibly occur in the alloy layer BM (in a portion indicated by reference BR) as shown in FIG. 9A. Also, the alloy layer BM has another problem. When a high-temperature exposure test (e.g., a test in which device test target is left in an environment at a temperature of 150° C. for a given period of time) is performed, heat facilitates the flowing of atoms of metal, thus causing an enlargement of the area of the alloy layer BM, and in turn, an increase in the likelihood of occurrence of break-off.
Description is given with regard to the occurrence of “break-off,” which takes place when the metal bumps BP1 and BP2 made of different metals are used to form a bond between the chip 60 and the wiring board 50, as shown in FIG. 9A. However, “break-off” in such a conductive bump can possibly occur likewise even in the case of bonding using the same metal. For instance, if any one of eutectic solder (made up of tin (Sn) and lead (Pb)) and lead-free solder (e.g., made up of Sn, silver (Ag) and Cu) is used as a material for the conductive bump, the same or similar break-off can possibly occur, depending on temperature conditions or testing time, because of distribution of Sn—Pb or Sn—Ag—Cu alloy in the conductive bump, although such a local alloy layer BM as is shown in FIG. 9A is not formed.
In order to cope with such “break-off,” a method using an underfill resin for the fixing of the chip to be mounted and the wiring board is widely adopted. FIG. 9B shows an example of the case. As shown in FIG. 9B, bumps BP to function as electrode terminals provided on the chip 60 to be mounted (the pad portions 62 exposed from the protection film 61) are connected by flip chip bonding to the pad portions 52 exposed from the protection film 51 of the wiring board 50. Then, an underfill resin 70 is filled into a gap between the wiring board 50 and the chip 60, and cured in the gap. By this method, the reliability of connection is improved, since the chip 60 and the wiring board 50 are integrally formed via the underfill resin 70.
However, the following problems arise. The method requires a process for filling the underfill resin 70 into the gap between the wiring board 50 and the chip 60, and hence causes a problem of an increase in man-hours and a rise in cost. Additionally, baking (heat treatment), which is performed to cure the underfill resin 70, often leads to a shrinkage in the underfill resin 70, so that the wiring board 50 is warped at its edges toward a chip mounting surface, as shown in FIG. 9B, due to the fact that the coefficient of thermal expansion of the underfill resin 70 is different from that of the wiring board 50. Further, delamination of the chip 60 may possibly occur depending on the degree of warp, thus causing deterioration in the reliability of connection.